It is often useful to utilize chip design application software to layout and plan new chips. This chip design application software is typically configured to aide the user in keeping track of resource requirements of particular modules. Furthermore, chip design application software also allows users to assign chip resources to particular modules.
However, chip design software applications typically have minimal graphical support. They usually are not capable of supplying the user with a graphical display representing a current status of the layout of the resources on a chip. Chip designers are typically required to manually and textually track their layout decisions with minimal graphical support. Further, typical software packages do not give graphical representations of possible placement of resources for unplaced user modules. Additionally, typical software packages also do not provide automated possible placements for user module resources.
Using the conventional art, a chip designer examines the vacant hardware resources and manually determines which hardware resources can be used for which user modules. This task involves manually determining the set of resources available in a hardware block and comparing them to the resources needed for a user module. This manual test is very technically complex and user-prone. Further, because possible placements require a great deal of manual effort, optimization through iteration trial and error is typically never accomplished.